TimingAnalyzer Schedulability analysis/Trace visualization A graphic diagram offers an intuitive overview of the timing. It gives the application engineer a better understanding of program processing in the ECU. It also considerably reduces the risk of creating unreliable systems. The foundation for designing real-time systems is an analysis of the schedulability of tasks (schedulability analysis). Systems that employ a real-time operating system, such as the OSEK/VDX oper-ating system or AUTOSAR OS, consist of tasks and interrupt service routines (ISR). Schedulability analysis shows whether a task or ISR could miss its deadline when all circumstances are taken into considerations. Functions In the analysis, the TimingAnalyzer studies the timing of both tasks and ISRs. A special algorithm considers mutual interactions resulting from use of the “resource” operating system service. In the TimingAnalyzer you can input the time with which a task or ISR occupies the specific OSEK resource. Properties and Advantages The TimingAnalyzer simulates scheduling tables and computes schedulability. The analysis is performed for each task and ISR with the information: priority, period, execution time and dead-line. The graphic representation simulates a possible task switching sequence. The simulated schedule can be examined by zooming in and measuring time intervals. Bitmaps of the graphic diagram can be saved for documentation purposes. Various algorithms from scheduling theory may be selected. In the default setting, the best algorithm is selected for a given data record. 4/6 By using the TimingAnalyzer you can avoid the difficult and time-consuming work involved in determining worst case timing situa-tions, Special functions > Schedulability analysis > Graphic simulation of schedules > Import and display of emulator traces which is usually done by testing. The TimingAnalyzer is a tool for integrating familiar software components into a runnable system. The time savings in terms of program creation and the test phase translate into cost savings as well. Processor use is computed and output as a percentage. Processor use is optimized by modifying calibration parameters, leading to an efficient design that conserves on hardware resources. Analysis example in the TimingAnalyzer